This invention relates generally to semiconductor chip package assembly, and in particular to flip chip package assembly. More specifically, the invention relates to a low-K Si die flip chip package incorporating warpage control structures and methods of their assembly in a semiconductor low-K Si die flip chip package.
In semiconductor device assembly, a semiconductor chip (also referred to as an integrated circuit (IC) chip or “die”) may be bonded directly to a packaging substrate. Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is “flipped” onto its front surface (e.g., active circuit surface) so that the solder balls form electrical connections directly between the chip and conductive metal pads, pre-solder, or traces on a packaging substrate. Packages of this type are commonly called “flip chip packages.”
As advances in semiconductor technology further increase the speeds of silicon chips, a shift towards using Si die with a plurality of layers of low dielectric constant (low-K) material have been sought. Low-K material assists in the reduction of propagation delay because of the lower dielectric constant, thereby improving the electrical performance of low-K Si die. On the other hand, however, such low-K material is usually very brittle and has presented significant packaging problems (e.g., reliability).
In a conventional method for a flip chip package, a die and a packaging substrate are electrically connected and mechanically bonded in a solder joining operation. The die is aligned with and placed onto a placement site on the packaging substrate such that the die's solder bumps are aligned with electrical metal pads or pre-solder on the substrate. The substrate is typically composed of an organic material or laminate. Heat is applied causing the solder bumps to alloy and form electrical connections between the die and the packaging substrate. The package is then cooled to harden the connection.
An underfill is then applied in order to enhance the mechanical bonding of the die and substrate. An underfill material, typically a thermo-set epoxy, is dispensed into the remaining space (or “gap”) between the die and the substrate. The underfill is then cured by heating.
Semiconductor packages are typically subject to temperature cycling during normal operation. In order to improve the thermal performance and reliability of the packages, heat spreaders are often used. A heat spreader may either be in an one piece heat spreader construction or in a two piece heat spreader construction (e.g., lid and stiffener). That is, a heat spreader may be composed of a lid connected to the substrate via a stiffener or may also have a form that allows for direct attachment to the substrate, such as through edges or legs that descend from the flat piece overlying the die to contact the substrate. In either case, it is referred to herein as a heat spreader.
If a two piece heat spreader is used, the stiffener may be placed around the die on the substrate where it is bonded with a heat curable organic adhesive. The stiffener (also sometimes referred to as a “picture frame”) is typically a flat piece of high modulus metal having substantially the same dimensions as the package substrate with a window in its center to clear the die. The purpose of the stiffener is to constrain the substrate in order to prevent its warpage or other movement relative to the die, which may be caused by thermal cycling during reliability testing or field operation. Such movement may result from the different coefficients of thermal expansion (CTE) of the die and substrate materials, and may produce stress in the die or the package as a whole that can result in electrical and mechanical failures.
An one piece heat spreader or a lid of a two piece heat spreader is typically composed of a high thermal conductivity material and has substantially the same dimensions as the package substrate. The one piece heat spreader is typically attached to the die with a thermally conductive organic adhesive material as well as to the substrate with an organic adhesive. As for a two piece heat spreader, the lid is typically attached to the die with a thermally conductive organic adhesive material and to one side of the stiffener with an organic adhesive. The other side of the stiffener is attached to the substrate with also an organic adhesive. The purpose of the heat spreader is to disperse the heat generated during the die's operation and to keep the integrated circuit's junction temperature low.
A problem with such flip chip package constructions is that during the cool down from the solder joining temperature and the underfill curing, the whole package is highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate and die materials. Shrinkage of the substrate, typically an organic material having a relatively high CTE is much more than that of the die, which typically is silicon-based and has a much lower CTE. The high stress experienced by these bonded materials during cooling may cause them to warp or crack and cause the package structure to bow. This problem is exacerbated in the case of a relatively large die, for example one 400 mm2 or larger, attached to an organic substrate. Consequently, the bow of the package may exceed the co-planarity specification for flip chip packages.
With the introduction of low-K Si dice and future extra-low-K Si dice in flip chip packages, the problems experienced by conventional flip chip packages are of even greater significance. This is because, as compared to traditional dielectric materials in conventional silicon based dice, low-K dielectric materials are brittle and tend to crack under substantially less mechanical or thermal stress. As such, it is possible for the reliability of the low-K Si die to be compromised due to cracking of the low-K dielectric material. In addition, the mismatches in thermal expansion between the low-k dielectric material, silicon based die, heat spreader, and substrate can lead to delamination or collapse of the low-K material in the packaged low-K Si die during its manufacture or during its use in the field. Low-K Si die's susceptibility to cracking, delaminating, or collapsing of the low-K material is generally applicable to all sizes of dice. Consequently, lower yield, poorer reliability, and higher costs result in the manufacturing and use of both the low-K Si dice themselves as well as the overall low-K Si die flip chip packages.
Accordingly, what is needed are low-K Si die flip chip packages and packaging methods that control package warpage within acceptable limits for incorporation into electronic devices and that redistribute the package's internal stresses in enhancing both the low-K Si die and the low-K Si die flip chip package reliabilities.